Crystal managed ramp generator – EDN


This challenge originated from the necessity to produce a linear crystal-controlled ramp sign for an HP 8620C RF sweep oscillator. It’s impressed by a beforehand revealed ramp generator design [1]. That design although suffered from two points: it used a non-standard 16.384 MHz crystal oscillator and the autumn/return/blanking time of the ramp was zero.

To deal with the primary situation, the ramp generator described right here makes use of a regular 10 MHz clock permitting it to be built-in into an current check setup. Secondly, most tools requires a finite time to return to its preliminary state earlier than beginning a brand new sweep. The design introduced in Figures 1 and 2 (see beneath), overcame these points. The ramp generator part can be described first as its necessities drove the design of the clock generator.

Ramp Generator

The guts of the ramp generator is a 12-bit digital-to-analogue converter (DAC) pushed by binary counters. The DAC is a discrete R-2R kind as on the time of improvement an acceptable IC DAC was not obtainable. That is pushed by a financial institution of AND gates (three 74HC08), that are in flip driver by two 74HC393 twin 4-bit binary counters—one half of 1 just isn’t used. 12 bits provides a most attainable depend of 4096 states. A simplified schematic of the ramp generator is proven in Determine 1.

Determine 1 Ramp generator schematic.

To outline the blanking time, the DAC solely outputs a ramp for the primary 4,000 states. For the remaining 96 its output is held at 0 V, which is adequate time for the HP 8620C to return to the beginning frequency and settle. In the course of the ramping section the AND gates go the counter outputs to the DAC. In the course of the blanking section the AND gates are pushed low, pulling the inputs to the DAC low and its output to 0 V. A two-input OR gate (two 1N4148 diodes and a resistor) and a five-input NAND gate (74HC30 with three of its enter tied collectively) monitor the output of the counter and drive the widespread enter of the AND gates throughout blanking. There’s additionally an inverter shaped from a NOR gate (74HC02) to provide a constructive going blanking pulse which can be utilized to modulate the Z-input of an oscilloscope.

Wow the engineering world together with your distinctive design: Design Concepts Submission Information

A resistor-diode swap on the output of the DAC can be enabled throughout the blanking section to drag the DAC’s output to 0 V. In the course of the ramping section, the DAC’s output is amplified by an op-amp to supply the ten V sign required by the HP 8620C.

The ramp generator may be switched between free-running and exterior set off—it’s proven in exterior set off mode in Determine 1. In set off mode, a set-reset latch composed of two NOR gates detects the rising fringe of the blanking output to reset the 12-bit counter. Solely when an exterior set off arrives does the set-reset latch reset in order that the 12-bit counter can begin counting once more.

Clock Generator

An inside or exterior 10 MHz crystal reference is split right down to 12 separate frequencies and chosen by a 12-way rotary swap for feeding to the ramp generator. For the reason that ramp generator solely produces a ramp output for the primary 4,000 states as an alternative of 4,096, the usual 2, 5, and 10 division ratios of a 74HC390 twin decade counter can be utilized as proven in Determine 2. The 74HC390 consists of two separate divide-by-2 and divide-by-5 counters, that are configured as proven. The clock frequency at every output is indicated together with its corresponding sweep time in brackets.

Determine 2 Clock generator schematic.

An exception to the above rationalization is the 1 ms sweep time, which requires a 4 MHz clock. The primary divider stage is subsequently a divide-by-2.5. That is achieved by tapping off the least-significant little bit of a divide-by-5 counter. For each 5 enter pulses it produces two output pulses: 000, 001, 010, 011, 100, 000, 001, 010, 011 and so forth. The obligation cycle of this 4 MHz clock will differ cycle-to-cycle resulting in minor jitter at 1 ms sweep time, however this may solely present itself on the least important little bit of the ramp generator counter so just isn’t important. Different divide-by-2.5s can be found which have a set 50% obligation cycle, however are extra advanced [2]


The measured output waveforms are proven in Determine 3 for the ramp and blanking outputs, the place they are often seen to have a precise interval of 100 ms and the ramp has a excessive linearity.

Determine 3 Measured waveforms: ramp output in yellow, blanking pulse in inexperienced.

The whole ramp generator was constructed on stripboard and housed in an tools case with built-in energy provide to type a helpful piece of laboratory tools.

[1] Neil Johnson, “Ramp Generator”, On a regular basis and Sensible Electronics, July 1995, pp. 546-550.

[2] Yongping Xia, “Divide by 2.5”, Electronics World + Wi-fi World, December 1991, pp. 1051.

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